Definitions

Term

Definition

Add/Drop Multiplexers (ADM)

Plesiochronous and lower bit rate synchronous signals can be extracted from or inserted into high speed SDH bit streams by means of ADMs. This feature makes it possible to set up ring structures, which have the advantage that automatic back-up path switching is possible using elements in the ring in the event of a fault.

Ageing

The systematic change in frequency of an oscillator with time. NB - It is the frequency drift when factors external to the oscillator environment, power supply, temperature, etc.) are kept constant. An ageing value should always be specified together with the corresponding duration.

Alignment Jitter

The short-term variations between the optimum sampling instants of a digital signal and sampling clock derived from it.

Autonomous PRC

Autonomous PRC's are PRC's with one or several (up to three) Caesium tubes incorporated in the PRC and used as a reference for an SSU. The free run accuracy of PRC must be 1 x 10-11 according to G.811 or EN 300 462-6-1.

Asynchronous Mode

A mode where clocks are intended to operate in free running mode.

Bilateral

A Synchronisation link where the corrective action to maintain locking is active at both ends of the link.

Clock

An equipment that provides a timing signal. NB - The word "clock" generally means, when used for Synchronisation networks, the generator of the frequencies which will be used to synchronise the network.

Clock-Source Quality-Level

The clock-source quality-level of a SDH Equipment Clock (SEC) or Stand Alone Synchronisation Equipment (SASE) is defined as the grade of clock to which it is ultimately traceable; i.e. The grade-of-clock to which it is synchronised directly or indirectly via a chain of SEC's, and SASE's however long this chain of clocks is. For example, the clock-source quality-level may be a PRC complying with G.811 or EN 300 462-6-1, or it may be a Slave Clock in holdover-mode, complying with G.812 or EN 300 462-4-1 or EN 300 462-7-1, or a EN 300 462-5-1 Clock in holdover or free-run.

The clock-source quality-level is essentially, therefore, an indication only of the long-term accuracy of the Network Element (NE) Clock.

Controlling RNC

A role an RNC can take with respect to a specific set of UTRAN access points. There is only one Controlling RNC for any UTRAN access point. The Controlling RNC has the overall control of the logical resources of its UTRAN access points.

Degradation Of Digitally Encoded Analogue Information

Degradation of digitally encoded analogue information may occur as a result of phase variation of the reconstructed samples in the digital to analogue conversion device at the end of the connection. This may have significant impact on digitally encoded video signals.

Digital Cross-Connexts (DXC)

This network element allows mapping of PDH tributary signals into virtual containers as well as switching of various containers up to and including VC-4.

With the perceived vulnerability of the GPS system, and its own propagation and reception limitations, renewed interest in LORAN applications and development has appeared. Enhanced LORAN, aka E-LORAN or eLoran, comprises an advancement in receiver design and transmission characteristics which increase the accuracy and usefulness of traditional LORAN, with reported accuracy as high as 8m, competitive with unenhanced GPS. eLoran also includes additional pulses which can transmit auxiliary data such as DGPS corrections or UTC information. E-LORAN receivers now use "all in view" reception, incorporating signals from all stations in range, not solely those from a single GRI, incorporating time signals and other data from up to 40 stations. These enhancements in LORAN make it adequate as a substitute for scenarios where GPS is unavailable or degraded.

Error

Errors may occur at points of signal regeneration as a result of timing signals being displaced from their optimum positions in time.

An Access Point Base Station - sometimes called a 'femtocell', is a scalable, multi-channel, two-way communication device extending a typical base station by incorporating all of the major components of the telecommunications infrastructure. A typical example is a UMTS access point base station containing a Node-B, RNC and SGN with only an Ethernet (or ATM/TDM) connection to the Internet or Intranet. Application of VoIP allows such a unit to provide voice and data services in the same way as a normal base station, but with the deployment simplicity of a WiFi access point.

Fractional Frequency Deviation

The difference between the actual frequency of a signal and a specified nominal frequency, divided by the nominal frequency.

Frame Aligner

Where a frame aligner is used, a slip will consist of the insertion or removal of a consecutive set of digits amounting to a frame. In the case of frame structures defined in Recommendation G.704 the lip can consist of one complete frame. It is of importance that the maximum and mean delays introduced by the frame aligner should be as small as possible in order to minimise delay. It is also of importance that, after the frame aligner has produced a slip, it should be capable of absorbing substantial further changes in the arrival time of the frame alignment signals before a further slip is necessary.

Free Run Mode

A clock is said to be in free run mode when its output signal is strongly influenced by the oscillating element and not controlled by servo phase-locking techniques. In this mode the clock has never had a network reference input, or the clock has lost external reference and has no access to stored data, that could be acquired from a previously connected external reference. Free-run begins when the clock output no longer reflects the influence of a connected external reference, or transition from it. Free-run terminates when the clock output has achieved lock to an external reference.

Frequency Accuracy

The maximum magnitude of the fractional frequency deviation for a specified time period. NB - The frequency accuracy includes the initial frequency offset and any ageing and environmental effect.

Frequency Departure

An underlying offset in the long-term frequency of a timing signal from its ideal frequency.

Frequency Drift

The rate of change of the fractional frequency deviation from a specified nominal value, caused by ageing and external effects (radiation, pressure, temperature, humidity, power supply, load, etc.).
NB
- The external factors should always be clearly indicated
- The frequency drift includes not only the linear frequency drift rate but also any other higher order frequency drift.

Frequency Stability

The spontaneous and/or environmentally caused frequency change within a given time interval.
NB - It is generally distinguished between systematic effects such as frequency drift effects (caused by radiation, pressure, temperature, humidity, power supply, charge, ageing, etc.) and stochastic frequency fluctuations which are typically characterised in time domain (special variances have been developed for the characterisation of these fluctuations, such as Allan variance, modified Allan variance and Time variance) and/or frequency domain (one-sided spectral densities).

Frequency Standard

A generator, the output of which is used as a frequency reference.

The Galileo positioning system is a proposed satellite navigation system, to be built by the European Union (EU) as an alternative to GPS (which is controlled by the United States military) and the Russian GLONASS. The system should be operational by 2010, two years later than originally anticipated.

Hold-In Range

The largest offset between a slave clock's reference frequency and a specified nominal frequency, within which the slave clock maintains lock as the frequency varies arbitrarily slowly over the frequency range.

Holdover Mode

An operating condition of a clock which has lost its controlling reference input and is using stored data, acquired while in locked operation, to control its output. The stored data are used to control phase and frequency variations, allowing the locked condition to be reproduced within specifications. Holdover begins when the clock output no longer reflects the influence of a connected external reference, or transition from it. Holdover mode terminates when the clock is once again controlled by an external reference and reverts to locked mode condition.

High Watermark

The upper limit in a buffer above which the data is not allowed to go. Normal process is that if the data reaches the high watermark, the clock-out frequency is speeded up so that the buffer begins to empty. Causes loads of wander.

Ideal Operation

This category of operation reflects the performance of a clock under conditions in which there are no impairments on the input reference timing signal.

Intra-Nodal Synchronisation

The purpose of intra-nodal Synchronisation is to supply a Synchronisation reference signal to all pieces of equipment co-located e.g. In one building. The reference signals are generated in a node clock which is usually a SASE with a quality according to G.812 or EN 300 462-4-1. The SASE is synchronized to a reference signal coming from a PRC via inter-node Synchronisation transport. G.803 or EN 300 462-2-1 recommends that intra-node Synchronisation distribution should be in the form of a logical star. I.e. Equipment Synchronisation links should not be daisy chained.

Intrinsic Jitter

See "J" (jitter)

Jitter

The short-term variations of the significant instants of a timing signal from their ideal positions in time (where short-term implies that these variations are of frequency greater than or equal to 10 Hz).

Network node interface jitter requirements are given in G.823, G.824 and G.825 and EN 300 462-3-1 and EN 302 084 and fall into two basic categories:
- specification of the maximum permissible jitter at the output of hierarchical interfaces;
- sinusoidal jitter stress test specifications to ensure the input ports can accommodate expected levels of network jitter.

Additional jitter requirements for individual equipment may be found in the appropriate equipment Recommendations.

Jitter Tolerance

Every digital input interface must tolerate a certain amount of jitter before bit errors or synchronisation errors occur. Tolerance masks are therefore specified for the permissible jitter amplitudes at various jitter frequencies.

Jitter Transfer

If the input signal to a network element contains jitter, jitter will also be present at the output. The jitter transfer function (JTF) of a network element indicates the degree to which the output is affected by the input jitter, ie . whether the jitter is amplified or attenuated. Passage through the network element normally suppresses the high-frequency jitter components, with the low-frequency components appearing unchanged at the output. It is possible that slight amplification of the input jitter may occur. This may result in an accumulation of jitter, eg . in a chain of regenerators, which may exceed the maximum tolerable jitter value leading to transmission errors.

Jitter Types:

Intrinsic Jitter

Jitter at the output of a device that is fed with a jitter free input signal.

Mapping Jitter

Mapping of asynchronous tributary signals into synchronous transport signals requires bit stuffing in order to match the bit rates. This results in mapping jitter when the signal is demapped .

Pattern Jitter

Distortion in the digital signal leads to so-called inter-symbol interference, or time-domain impulse crosstalk. This results in interference between consecutive pulses in a digital signal which leads to jitter that is pattern-dependent.

Pointer Jitter

If the SDH transmission bit rates are not synchronous, the timing of the transported payload containers must be matched to the outgoing frame. This is done by incrementing or decrementing the pointer by one unit. This shifts the payload signal by 8 or 24 bits, corresponding to a phase hit of 8 or 24 UI.

The output clock must be smoothed in a similar way to the stuffing process. In this case though, must larger phase hits must be smoothed out much less frequently. The residual jitter therefore has larger amplitudes and lower frequency components.

Stuffing and Wait Time Jitter

During multiplexing, non synchronous digital signals must be matched to the higher bit rate system by the insertion of stuffing bits. These stuffing bits must be removed when the signal is demultiplexed . The gaps which thus occur are equalised out by means of a smoothed clock signal. This smoothing is, however imperfect, so stuffing and wait-time jitter occurs.

Local Loop

The part of the telephone line from a subscriber's premises to the telephone company's local exchange.

Local Node

A synchronous network node which interfaces directly with customer equipment.

Locked Mode

An operating condition of a slave clock in which the output signal is controlled by an external input reference such that the clock's output signal has the same long-term average frequency as the input reference, and the time error function between output and input is bounded. Locked mode is the expected mode of operation of a slave clock.

Low Watermark

The lower limit in a buffer below which the data is not allowed to go . Normal process is that if the data reaches the low watermark, the clock-out frequency is slowed down so that the buffer begins to fill.

Mapping Jitter

See "J" (jitter)

Master Clock

"A generator which generates an accurate frequency signal for the control of other generators"The Master Clock in a telecom network is known as a Primary Reference Clock or PRC.

Master Slave Mode

A mode where a designated master clock is used as a frequency standard which is disseminated to all other clocks which are slaved to the master clock.

Measurement Reference Timing Signal

A timing signal of specified performance used as a time base for clock characterisation measurements. The basic assumption is that its performance must be significantly better than the clock under test with respect to the parameter being tested, in order to prevent the test results being compromised. The performance parameters of the frequency standard must be stated with all test results.

Mutually Synchronised Mode

A mode where all clocks exert a degree of control on each other.

Murphy's Law

If something can go wrong it will.

Email us with you examples. We will publish the good ones. Here's a few to get started:
i ) the repair technician will accidentally remove the working PSU instead of the faulty one.
ii) major network failures only happen when potential clients are in the NMC.

Network Synchronisation

A generic concept that depicts the way of distributing a common time and/or frequency to all elements in a network.

Net-Head

Engineer involved with packet based IP data, routers etc. who does not understand the necessity for synchronisation . Beware VoIP and other CBR traffic over your packet environment.

Node Clock

A clock distributing Synchronisation to one or more synchronised equipment.

Noise Tolerance

The ability of a network element e.g. SSU to withstand a noisy input signal and still perform to specification.

Pattern Jitter

See "J" (jitter)

Phase Transient

Perturbations in phase of limited duration. E.g. Pointers on an E1 out of an SDH network.

Phase Variation

Phase variation is commonly separated into three components: jitter, wander and effects of frequency offsets and drifts. In addition, phase discontinuities due to transient disturbances such as network re-routing, automatic protection switching, etc., may also be a source of phase variation.

Plesiochronous Mode

A mode where the essential characteristic of time scales or signals such that their corresponding significant instants occur at nominally the same rate, any variation in rate being constrained within specified limits.

Pointers

The user of pointers gives SDM networks a distinct advantage over the plesiochronous hierarchy. Pointers are used to localise individual virtual containers in the payload of the synchronous transport module. The pointer may directly indicate a single VC-n virtual container from the upper level of the STM-1 frame. Chained pointer structures can also be used. The AU-4 pointer initially indicates the VC-4 overhead. Three further pointers are located at fixed positions in the VC-4; these indicate the start of the three VC-3 virtual containers relative to the VC-4.

SDH multiplexers are controlled from a highly accurate central clock source running at 2.048 MHz. Pointer adjustment may be necessary if phase variations occur in the real network or if the connection is fed through the networks of different providers. The AU pointer can be altered in every fourth frame with prior indication. The virtual container is then shifted by precisely 1byte (VC-12) or 3 bytes (VC-4). Pointer activity is an indication of clock variations within a network.

If the pointer is shifted to a later point in time the byte (VC-12) or three bytes (VC4) immediately following it will be ignored (negative justification). If the transmitting source is in advance of the actual clock, space for extra capacity must be provided. This negative justification takes place in spare byte/s in the pointer overhead, the V3 byte for a VC-12 and the three H3 bytes for a VC4. If a further clock adjustment is not made, this configuration will be propagated throughout the network. This allows, on the one hand, the free insertion in time of user signals into the next higher frame structure in the form of virtual containers without the need for larger buffers. On the other hand, changes in the phase location of the virtual container relative to the superior frame can be corrected by appropriate pointer actions. Such changes and shifts in phase can be caused by changes in propagation delay in the transmission medium or by non-synchronous branches in the real network. When a multiplex bundle is resolved, pointer procedures make it possible to immediately locate every used channel from each STM-N frame, which considerably simplifies drop and insert operations within a network node.

 Pointer Jitter

See "J" (Jitter)

Pseudo-Synchronous Mode

A mode where all clocks have a long-term frequency accuracy compliant with a primary reference clock as specified in G.811 or EN 300 462-6-1 under normal operating conditions. Not all clocks in the network will have timing traceable to the same PRC.

PRC Autonomy Period

The PRC Autonomy (Period) is the period of time over which a clock, after it disqualified all its reference inputs, can restrict its phase drift within the bounds given by the network limits for Synchronisation signals.

The notion of "PRC Autonomy Period" sets a quality parameter for a clock. Knowing the PRC Autonomy Period of a clock, one can determine the following:
- are multiple references to the SSU necessary? If the PRC Autonomy Period is longer than the time it takes to repair a failure in the case of a single reference, operation with a single reference is sufficient;
- how much time is available for a reference switch? If the PRC Autonomy Period is very long, one can make reference switches manually after judging the impairments and consequences. On the other hand shorter PRC Autonomy Periods require some kind of automatic reference switch process, which can be from a central manager (generally a slower process) or made locally by the clock itself (generally a faster process);
- what staffing levels are required to maintain the Synchronisation network? Do they need to be, for example, on a 24x365 or 8x5 sufficient?

The PRC Autonomy Period can be used to classify all SSU's in a Synchronisation area. The purpose of such classification is to be able to provide a hierarchy, based on the above defined "PRC Autonomy Period", among the SSU's in the Synchronisation network. A division of SSU's according to their PRC Autonomy Period, the number of Classes and their boundaries, will in general turn out to be different for different operators. Depending on the size of the Synchronisation areas, the number of SSU's per area and their quality. In most cases two Classes will suffice, but more (or fewer) Classes are possible.

In general one should avoid using an SSU of a "lower Class of PRC Autonomy" to provide the active reference for an SSU of a "higher Class of PRC Autonomy". This means that in a tree diagram of the SSU network, the PRC's are at the top and that in downward direction the SSU's are ordered according to their PRC Autonomy classification; the best ones close to the top, the lowest at the bottom of the tree.

The restoration mechanism for most SSU's will in general be automatic, based on local decisions by the SSU's themselves. All SSU's support a reference selection mechanism locally controlled by pre-programmed priorities (in addition they may also support other selection mechanisms).

PRC-Level

PRC-Level refers to the collection of PRC compliant clocks in an operator domain that are the master clocks for the different Synchronisation areas when the Synchronisation network does not experience failures.

E.g. G 201 793 provides more information.

The PRC-Level determines the way in which a certain operator domain is divided into Synchronisation areas. In each Synchronisation area one PRC is active at any moment (but additional stand-by PRC's can be part of a Synchronisation area). Two strategies can be followed to determine the size of each Synchronisation area. Strategy I is to make one big Synchronisation area and strategy II is to make each office a separate Synchronisation area. In fact, these two strategies can be considered as "extremes" on a continuous scale. Actual sizes of Synchronisation areas can be anywhere in between these "extreme" positions.

Strategy I (one large Synchronisation area covering the whole operator domain) has the advantage that the number of Synchronisation areas that an end-to-end traffic connection has to cross is minimised and hence the impact on controlled octet slip-rate performance (as defined in ITU-T Recommendation G.822) under normal conditions is minimised . However, the Synchronisation network is more complex. Therefore it is harder to engineer and also the Synchronisation trails become longer, hence more susceptible to impairments and wander accumulation (which may eventually have a negative effect on the octet-slip rate).

Strategy II (each telecommunication office forms a Synchronisation area) makes the engineering of each Synchronisation area almost trivial. The Synchronisation network will be very reliable, since the length of the Synchronisation trails is reduced to some (dedicated) intra-office cabling.

Generally, for an actual Synchronisation network a strategy somewhere between I and II is selected, i.e. Some (major) nodes have a PRC supplying the Synchronisation for a certain sub-domain of the total operator domain. Networks closer to a strategy II implementation have shorter, thus more reliable, Synchronisation trails and also have smaller, hence easier to engineer, Synchronisation areas. Networks closer to a strategy I implementation have fewer Synchronisation areas, hence fewer pseudo-synchronous area boundary crossings in end-to-end connections and fewer installed PRC clocks.

Pull-In Range

The largest offset between a slave clock's reference frequency and a specified nominal frequency, within which the slave clock will achieve locked mode.

Pull-Out Range :

The offset between a slave clock's reference frequency and a specified nominal frequency, within which the slave clock stays in the locked mode and outside of which the slave clock cannot maintain locked mode, irrespective of the rate of the frequency change.

Radio Controlled PRC

Radio-controlled PRC's are PRC's which use remote Caesium tubes, e.g. In the satellites of the GPS navigation system. In this case radio signals are generated on the basis of Caesium tubes, received at the location of the PRC and used as the reference signal for an SSU. Two types of radio controlled PRC's exist, land based and satellite based radio-controlled PRC's . Only satellite based PRC's are available worldwide.

The free run accuracy of PRC must be 1 x 10-11 according to G.811 or EN 300 462-6-1.

Reference Timing Signal

A timing signal of specified performance that can be used as a timing source for a slave clock.

Retimer Function

A Retimer allows the retiming of traffic (E1) data so that this data is timed by another clock rather than by its own clock source. This function can be implemented by writing a recovered signal into an elastic store (buffer) and time the output of that elastic store with another clock source, e.g. SDH line clock or local PRS (GPS) or SSU.

Retimers are available in different forms:-
- Stand-Alone - Typically 1U 19" or half rack free standing, they can be easily deployed locally to the trib launch point.
- Built into the SSU/BITS/SASE - Multiple channel retimer cards are fitted in the place of output amplifier cards.
- Built into the multiplexer - The retimer function can be activated in the output E1 trib .

Normally, in the absence of retiming, the rate of the outgoing signal is equal (when measured over a long enough time) to the rate of the incoming signal; in the case of retiming this relationship disappears. This means that data will be lost each time the phase difference between the 2 Mbit /s where it is mapped into a VC12 and the NE clock of the desynchronising node is larger than the buffer space of the retiming buffer. In the event of a frequency offset, this will lead to continuous buffer slips.

SEC-Level

SEC-Level refers to the collection of SEC compliant clocks in a Synchronisation area and their interconnections. SSU's are not part of the SEC-Level.

The SEC-Level consists of many separated islands of SDH equipment with SEC clocks built in. Each island is called an "SEC sub-network". Within the SEC sub-network automatic restoration is mandatory because the PRC Autonomy Period of an SEC is typically well below 1 minute. Restoration based on local SEC decisions is the fastest method.

SEC Sub-network

SEC sub-network refers to a collection of SEC clocks in SDH network elements interconnected by STM-N reference carriers. When engineering the synchronisation in a SEC sub-network, the directly connected SSU's need also to be considered.

Serving RNS

A role an RNS can take with respect to a specific connection between an UE and UTRAN. There is one Serving RNS for each UE that has a connection to UTRAN. The Serving RNS is in charge of the RRC connection between a UE and the UTRAN. The Serving RNS terminates the Iu for this.

SDH Transport Mechanism

The process of transporting PDH and ATM signals over the SDH network is called mapping. The container is the basic package unit for tributary channels. A special container (C-n) is provided for each PDH tributary signal. These containers are always much larger than the payload to be transported. The remaining capacity is used partly for justification (stuffing) in order to equalise out timing inaccuracies in the PDH signals. Where synchronous tributaries are mapped, fixed fill bytes are inserted instead of justification bytes. A virtual container (VC-n) is made up from the container thus formed together with the path overhead (POH). This is transmitted unchanged over a path through the network. The next step towards formation of a complete STM-N signal is the addition of a pointer indicating the start of the POH. The unit formed by the pointer and the virtual container is called an administrative unit (AU-n) or a tributary unit (TU-n).

Several TUs taken together form a tributary unit group (TUG-n); these are in turn collected together into a VC>. One or more AUs form an administrative unit group (AUG). Finally, the AUG plus the section overhead (SOH) forms the STM-N.

ATM signals can be transported in the SDH network in C11, C12, C3 and C4 containers. Since the container transport capacity does not meet the continually increasing ATM bandwidth requirement, methods have been developed for transmitting the ATM payload in a multiple (n) C-4 (virtual or contiguous concatenation). As an example, a quadruple C-4 can be transmitted in a STM-4.

Single Ended Synchronisation

A method of synchronising a specified Synchronisation node with respect to another Synchronisation node, in which Synchronisation information at the specified node is derived from the phase difference between the local clock and the incoming digital signal from the other node.

Slave Clock

A clock whose timing output is phase-locked to a reference timing signal received from a higher quality clock.

Slip

The repetition or deletion of a block of bits in a synchronous or plesiochronous bit stream due to a discrepancy in the read and write rates at a buffer.

Slips arise as a result of the inability of an equipment buffer store (and/or other mechanisms) to accommodate differences between the phases and/or frequencies of the incoming and outgoing signals in cases where the timing of the outgoing signal is not derived from that of the incoming signal.

Slips may be controlled or uncontrolled depending on the slip control strategy. Slips may occur in asynchronous multiplexes and various synchronous equipments. Given the specified levels of phase variation, slip occurrences may be minimised in asynchronous multiplexers by appropriate choice of justification and multiplexer buffer capacity within. For synchronous equipments, slip occurrences may be minimised by appropriate choice of buffer capacity as well as rigorous specification of clock performance. It should be noted that it is impossible to eliminate slips when there is a frequency difference between the incoming and outgoing timing signals. Controlled slip performance objectives for an international connection are given in Recommendation G.822.

Various forms of aligning equipment may be used to minimise the impact of slips. The following two forms of aligning equipment are suitable for the termination of digital signals:
- frame aligner;
- time slot aligner.

SSU-Level

SSU-Level refers to the collection of SSU compliant clocks in a Synchronisation area and their interconnections. SEC's are not part of the SSU-Level, but are considered to be transparent on connections between SSU's . Under failure free conditions, there is only one interconnected SSU-level in a Synchronisation area.

Standard Frequency

A frequency with a known relationship to a frequency standard.

Stressed Operation

This category of operation reflects the actual performance of a clock considering the impact of real operating (stressed) conditions. Stressed conditions include the effects of jitter, protection switching activity and the loss of the input reference timing signal.

Stuffing and Wait Time Jitter

See "J" (Jitter)

Synchronisation Area

The geographic area in which all equipment which needs to operate synchronously is synchronised to the one master-clock in that area.

Synchronisation Chain

An active interconnection of Synchronisation nodes and links.

Synchronisation Element

A clock providing timing services to connected network elements. This would include clocks conforming to G.811, G.812 and G.813 or EN 300 462-4-1, EN 300 462-5-1, EN 300 462-6-1 and EN 300 462-7-1.

Synchronisation Link

A link between two Synchronisation nodes over which Synchronisation is transmitted.

Synchronisation Interface

Synchronisation interfaces are synchronous (i.e. Normally PRC-traceable). The network limits for Synchronisation interfaces are specified using MTIE and TDEV parameters with values given in EN 300 462-3-1. The input jitter and wander tolerance of clock equipment ports is specified in G812 or EN 300 462-4-1 and EN 300 462-7-1 (for equipment containing an SSU function) and G.813 or EN 300 462-5-1 (for equipment containing an SEC function).

Synchronisation Network

A network to provide reference timing signals. In general, the structure of a Synchronisation network comprises Synchronisation network nodes connected by Synchronisation links.

Synchronisation Network Node

A group of equipment in a single physical location which is directly timed by a node clock. NB - A physical location may contain more than one Synchronisation network node.

Synchronisation Node

A Synchronisation node consists of an SSU and all co-located SEC's directly synchronised from that SSU.

Synchronisation Reference Chain

A specific Synchronisation chain to form the basis for simulations of jitter and wander in the Synchronisation network.

Synchronisation Sink

The destination of timing in a Synchronisation trail.

Synchronisation Source

The source of timing in a Synchronisation trail.

Synchronisation Traceability

A series of Synchronisation elements and Synchronisation trails, normally within a single SDH or PDH equipment domain.

Synchronisation Trail

The complete connectivity between Synchronisation element and a network element, or between two Synchronisation elements.

Synchronous Network

A network where all clocks have the same long-term accuracy under normal operating conditions.

Systematic Noise

Phase noise in the synchronisation caused by regular effects such as PLL activity or playout buffer wander.

Time

Time is used to specify an instant (time of the day) or as a measure of time interval. NB - The words time or timing, when used to describe Synchronisation networks, usually refer to the frequency signals used for Synchronisation or measurement.

Time Error Function

The time error of a clock, with respect to a frequency standard, is the difference between the time of that clock and the frequency standard.

Time Function

The time of a clock is the measure of ideal time as provided by that clock.

Time Scale

A system of unambiguous ordering of events. NB - This could be a succession of equal time intervals, with accurate references of the limits of these time intervals, which follow each other without any interruption since a well-defined origin. A time scale allows to date any event. For example, calendars are time scales. A frequency signal is not a time scale (every period is not marked and dated). For this reason "UTC frequency" must be used instead of "UTC".

Time Slot Aligner

Where a slot aligner is used, a slip will consist of the insertion or removal of eight consecutive digit positions of a channel time slot in one or more 64 kbit /s channel . Because slips may occur on different channels at different times, special control arrangements will be necessary in switches if octet sequence integrity of multiple time slot services is to be maintained.

Timing Loop

Also known as a "Sync Loop". This is a network condition where a slave clock providing Synchronisation becomes locked to its own timing signal. It is generally created when the slave clock Timing Information is looped back to its own input, either directly or via other network equipments. Timing loops should be prevented in networks by careful network design.

Timing loops must be prevented because all clocks in a timing loop are isolated from a PRC and are subject to unpredictable frequency instabilities. There is no simple way of detecting timing loops as no alarms are generated on their creation. They can go undiscovered until service is effected by poor slip or error performance leading to an investigation which will eventually locate the timing loop.

Timing Signal

A nominally periodic signal, generated by a clock, used to control the timing of operations in digital equipments and networks. Due to unavoidable disturbances, such as oscillator phase fluctuations, actual timing signals are pseudo-periodic ones, i.e. Time intervals between successive equal phase instants show slight variations.

Traffic Interface

Traffic interfaces may be synchronous (i.e. Normally PRC-traceable) or asynchronous (e.g. Meeting the frequency offset requirements of G.703 or ETS 300 166). Network jitter and wander limits are specified in G.823 and EN 302 084 and wander is specified using the MTIE and MRTIE parameters. Input jitter and wander tolerance is also specified in G.823, G.824 and G.825 or EN 302 084. This interface category can be further subdivided as follows:
- interface is not able to provide Synchronisation, and is not required to. An example is an interface supporting only 34,368 kbit /s or 139,264 kbit /s PDH signals according to G.703 or ETS 300 166;
- interface is not able to provide Synchronisation at the defined performance level, but nevertheless is used to provide timing to other network elements such as terminal equipment, remote concentrators, etc. Examples include 2048 kbit /s, 34, 368 kbit /s and 139,264 kbit /s PDH signals and leased lines transported on SDH, which may be subject to pointer justifications. G.803 recommends that these interfaces are not used for Synchronisation, but in some network applications there is little alternative;
- interface is able to provide Synchronisation at the defined performance level, in which case it is defined to be a Synchronisation interface. An example is STM-N interfaces. This sub-category may also include interfaces using the generic frame structures at PDH rates as described in ETS 300 337.

Transit Node

A synchronous network node which interfaces with other nodes and does not directly interface with customer equipment.

Type 43 Connector

Connector for 75 ohms 2.048 MHz and 2.048 Mbit /s signals. Sometimes known as BT43 after the original BT specification.

UMTS Core Network

Refers in this specification to an evolved GSM core network infrastructure or any new UMTS core network infrastructures, integrating circuit and packet switched traffic.

Unilateral

A Synchronisation link where the corrective action to maintain locking is only active at one end of the link.

Wander

The long-term variations of the significant instants of a digital signal from their ideal position in time (where long-term implies that these variations are of frequency less than 10 Hz).

NB - This definition does not include wander caused by frequency offsets and drifts.

Relevant wander requirements fall into the following categories:
i ) maximum permissible wander at the output of Synchronisation network nodes;
ii) stress tests to ensure that synchronous equipment input ports can accommodate expected levels of network wander;
iii) wander specifications for primary reference and slave clocks may include:
a) intrinsic output wander under locked conditions;
b) intrinsic output wander under free-running conditions;
c) output wander under stress test conditions;
d) wander transfer characteristic.

The existing requirements for the primary and slave clocks are given in G.811, G.812 and G.813 and EN 300 462-3-1, EN 300 462-4-1, EN 300 462-5-1, EN 300 462-6-1 and EN 300 462-7-1.

The purpose of this definition is not only to provide limits for the allowance wander accumulation along the transmission paths but also for the wander accumulation along the Synchronisation distribution paths arising from cascaded clocks.